Digital delay line tester

ABSTRACT

The present invention describes a tester for determining the value of unknown delay lines in the nanosecond and subnanosecond range. The unknown delay line is introduced into the circuit loop of a free-running square wave oscillator previously calibrated to a predetermined frequency. A change in oscillator frequency occurs which is a measure of the value of the delay introduced into the loop by the unknown line. Such delay may be calculated as a function of the calibration and delay line-measured frequencies. The present tester provides measurements with increased accuracy and rapidity over previous measuring techniques.

BACKGROUND OF THE INVENTION

In the design of electronic equipment and systems, delay lines arefrequently employed. Up until the present, the most reliable, accurateand accepted method of measuring delay lines made use of a pulsegenerator and a sampling oscilloscope. Such a method was satisfactoryfor the following reasons. The delay lines in use typically provided adelay greater than 10 nanoseconds. The pulse generators needed to obtainthe delay measurements were required to provide output pulses having 1.0nanosecond rise times. Such generators are relatively inexpensive andwidely available. Most users of the delay lines already had a samplingoscilloscope and the required parts to construct a test fixture. Thelatter fixture was relatively simple and parisitic reactive effects weresubstantially negligible.

More recently, the quest for increased speed in electronic systems hasled to the need for delay lines within the 1 to 5 nanosecond range, andeven a delay of 0.50 nanoseconds is possible. The above mentioned pulsegenerator/oscilloscope technique is not applicable to measurements ofsuch short lines. A number of problems arise when use of the lastmentioned technique is contemplated. Pulse generators are required withpulse rise times much less than 1.0 nanosecond and these are veryexpensive. The sampling oscilloscope and associated probes must haveextremely wide bandwidths. The parasitic effects which heretofore werenegligible, became important to the extent that the layout of the testfixture is now a critical factor. Moreover, the trace width of thesampling oscilloscope introduces considerable error in the measurements.Variations in the impedance of the delay line may interfere with theability to read the oscilloscope correctly. In addition, the process ofmaking such measurements is tedious and time consuming.

What is desired is a delay line tester useful in the nanosecond andsubnanosecond range which obviates the foregoing measurement problems.The digital tester of the present invention fills such a need and doesso with an inexpensive stand-alone unit providing measurements withgreatly increased accuracy and rapidity over previous measuring methods.

SUMMARY OF THE INVENTION

In accordance with the present invention there is provided a test-headcomprised of a free-running oscillator and a socket disposed within theoscillator loop and having a pair of terminals for connection to thedelay line under test. Initially, the last mentioned terminals are shortcircuited and with the implicit delay in the oscillator circuit itself,designated dc, the frequency, fc which is equal to 1/2dc is adjusted toa predetermined value, such as 100 MHz used in an actual operativeembodiment of the tester. The short circuit is then removed and theunknown delay line is connected between the socket terminals. Themeasured frequency of oscillation, fm, is then counted and the unknowndelay, dx, is calculated from a simple equation: ##EQU1## and theunknown delay is ##EQU2## where "dx" is in seconds and "fm", "fc" are inHz.

The foregoing equations are accurate provided that "dc" is reasonablysmall and the frequency counter reasonably accurate. Satisfactoryresults have been obtained with a "dc" equal to 10.0 nanoseconds and afrequency divider of 32,000 applied to the output frequencies of thetest-head oscillator. The divider derives its accuracy from a crystalsource which is 0.01% accurate. The division by 32,000 limits thecounter-size and sensitivity to reasonable numbers. Utilizing theseparameters, lines having delays in the order of 0.50 nanoseconds havebeen accurately measured.

The above-mentioned equation for the unknown delay "dx" is readilycalculated by a microprocessor incorporated into the tester. The unknowndelay value is displayed decimally in nanoseconds to two significantfigures to the right of the decimal point. The microprocessor thenrepeats the procedure, recalculating the unknown delay time 250 times asecond. The resulting display is a non-flickering, accurate,easy-to-read number accurate to ±10 picoseconds for unknown delays ofless than 3.0 nanoseconds.

Other features and advantages of the tester of the present inventionwill become apparent in the detailed description which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of the digital delay line tester ina calibration mode.

FIG. 2 is a simplified block diagram of the digital delay line tester inits operational mode.

FIG. 3 is a schematic diagram of the test head shown in FIGS. 1 and 2and adapted to receive the unknown delay line.

FIG. 4 comprises FIGS. 4A, 4B, 4C, which together form a detailedcircuit diagram of the delay line tester of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The digital delay line tester of the present invention is depicted inhighly simplified form in FIG. 1, which indicates a calibration mode.

The test head 10 provides a free-running oscillator implemented byinverter 12 and having an implicit delay which is manually adjustable bydelay means 14. In practice, the oscillator loop may be entered atterminals 16. In the calibration mode, the terminals 16 are shortcircuited by electrical conductor 18 and means 14 adjusted to vary thefrequency of the test head signal output. The oscillator signals out ofthe test head are applied to counters 20 which effect a frequencydivision of 32,000. The preset digital word 22 represents apredetermined frequency, such as 100 MHz used in an actual operativetester, divided by 32,000. The respective 13 bit digital wordsrepresenting the oscillator frequency and the predetermined calibrationfrequency are applied to the input terminals "A" and "B" of multiplexer24. Microprocessor 26 performs a select function of the two multiplexerinputs in accordance with its output signal to the SEL terminal ofmultiplexer 24. Comparator 27 compares 8 bit digital wordsrepresentative of the test head output frequency and the predetermined100 MHz calibration frequency. An LED indicator 28, driven by thecomparator circuits, will light when manual adjustment of delay means 14provides a test head output frequency equal to 100 MHz.

After calibration has been accomplished, an operational mode as depictedin highly simplified form in FIG. 2 is established. The electricalconductor 18 (FIG. 1) shorting terminals 16 is removed and the unknowndelay line 30 whose delay is to be measured by the tester is placedbetween terminals 16. The frequency of the output signals of the testhead are now a function of the unknown delay line 30 under test. As inthe calibrate mode, the frequency output of the test head is divided by32,000. The output of the divider and the preset digital word areapplied to respective input terminals of multiplexer 24. Microprocessor26 by virtue of its select function, constantly and alternately reads inthe test head frequency digital word representing the unknown delay lineand the preset digital word that corresponds to 100 MHz. Themicroprocessor 26 is programmed to solve the relatively simple equationsinvolving the last mentioned digital words and to display the decimalvalue of the delay of the line under test in display unit 32. In anoperative embodiment, the unknown delay value was displayed decimally innanoseconds, as seen in FIG. 2, to two significant figures to the rightof the decimal point. Recalculations by the microprocessor 26 at a rateof 250 times per second, result in a non-flickering number accurate to±10 picoseconds, for lines having delays less than 3.0 nanoseconds.

FIG. 3 provides an electrical schematic of the test head 10 shown insimplified form in FIGS. 1 and 2. With reference to FIG. 3, afree-running square wave oscillator utilizes transistor 34 in aninverting common emitter configuration--equivalent to inverter 10 ofFIGS. 1 and 2. The oscillator loop includes a socket 36 having terminals16. Delay in the loop (with terminals 16 short circuited) is effected bythe implicit delay in transistor 34, the 50 ohm coaxial line 38, and thesetting of variable capacitor 40. In general, the length of the coaxialline 38 is chosen to generate an oscillation frequency of approximately100 MHz, the calibration frequency. A precise adjustment of the lastmentioned frequency is accomplished by manually varying the value ofcapacitor 40.

When the calibration frequency is realized, the short circuit betweenterminals 16 is removed, and the unknown delay line (30 in FIG. 2)connected between the last mentioned terminals. The oscillator frequencyis now directly proportional to the unknown delay. It should be notedthat the actual delay in the loop, designated "d", is half the period ofthe square wave cycle. Stated another way, the output frequency of thetest head is equal to 1/2d.

The Schottky diode 42 prevents saturation of transistor 34 and speeds upoperation. The shunt capacitors 44 interposed between the emitter oftransistor 34 and ground are of different values such that ac signalsover a wide frequency band will be by-passed to ground. Outputtransistor 46 performs a voltage level shifting function on theoscillator signals which make them ECL compatible with the testercircuits of FIG. 4 to which the signals are applied via coaxial line 48.

FIG. 4 is a detailed circuit diagram of an actual operative embodimentof the digital delay line tester of the present invention. Withreference to FIGS. 4A and 4C, the input circuits and counters will nowbe described.

INPUT CIRCUITS AND COUNTERS

The output of the test head is an ECL square wave signal appearing online 48. As noted hereinbefore, the signal is calibrated to 100 MHz witha short circuit across the terminals 16 of the test head socket 36. Line48 is a coaxial cable to minimize signal distortion. A counter 50comprised of counter units 50a, 50b, 50c, 50d, and 50e are depicted. Thecounter 50 is used in two different modes--count up and reset. Each ofthe counter units has a mode select line 52. The square wave outputsignal from the test head 10 is applied to the clock terminal CLK ofcounter 50a.

As seen in FIG. 4B, a microprocessor 54 is provided. All of the modeselect lines 52 of the counter 50 are connected in common and are undercontrol of the microprocessor 54. It should be observed that theprocessor elements (chips) are configured in a conventional manner. Withcontinued reference to FIG. 4B, element 56 is a programmable I/O, timerand RAM chip; element 58 is an 8 bit address latch; and PROM chip 60provides 512 bytes of programmable memory. Chip 56 handles allcommunication between the high speed counter 50 and microprocessor 54.Chip 56 has three ports which may be configured in many different ways.In the present application, ports A and B are used strictly as inputports and port C as an output (control) port. The respective mode selectlines 52 of counter 50 are controlled directly through port C, line PC3.

In the operative embodiment of FIG. 4, the microprocessor 54 utilized inthe tester operates with TTL signals, whereas as noted hereinbefore, thecounter units 50a-50e are ECL. Accordingly, signals from themicroprocessor must be translated to ECL levels if they are to controlthe counter 50. The chip 62 comprised of a plurality of gates performsthis level-shifting function for the respective microprocessor signalsappearing on terminals PCO:3 of element 56. The mode select signal fromelement 56, port C, PC3, after being translated in chip 62, appears online 64 and is applied via buffer 66 in common to the input terminals ofa plurality of NOR gates 68. The respective outputs of the lastmentioned gates are applied to the mode select lines 52 of the counter50.

NOR gates 70a, 70b, 70c, and 70d serve two purposes. First, theypropagate the most significant bit of the last counter into the clockinput of the next stage when the counter is in a count-up mode. Forexample, the output on line 72 of counter unit 50a is applied via gate70a to the clock input CLK of counter 50b. Moreover, gates 70a-70denable a clock pulse from the microprocessor 54, clock terminal CLK intothe respective clock CLK inputs of the counter units 50a-50e during thereset thereof. The microprocessor clock is derived from a stable 4 MHz(±0.01%) crystal source 74 for use by the microprocessor 54 and thecounter 50. The 4 MHz clock is further counted down by divider element76 for use by processor chip 56, as will be considered hereinafter. Itshould be noted that the 4 MHz clock pulses on line 78 are also TTL andmust be level shifted by gate 80 and are then buffered by AND gate 82such that the output of the last mentioned gate on line 84 is applied incommon to an input terminal of each of the NOR gates 70a, 70b, 70c, 70d.The respective outputs of the last mentioned NOR gates are applied tothe clock terminals of counters 50b, 50c, 50d and 50e.

A multiplexer 86 with units 86a, 86b, 86c and 86d are provided. Theoutputs of counter units 50 are applied respectively to the "A" inputsof multiplexer 86. The "B" inputs of the multiplexer 86 are hardwired toreceive the bits of a preset binary word, namely "0110000110101",derived from the 100 MHz calibration frequency divided by 32,000. Eitherthe "A" inputs or the "B" inputs may be selected by the commonRUN/CALIBRATE line 88. When the RUN/CALIBRATE switch 90 is in theCALIBRATE position, the counter outputs are selected as inputs to themultiplexer 86. When the switch 90 is in the CALIBRATE-CHECK position,the hardwired digital word is the selected input to the multiplexer 86.When switch 90 is placed in the RUN position, the multiplexer selectline 88 is under control of microprocessor 54. The multiplexer 86provides a 13 bit digital word output that represents a frequency to themicroprocessor. The multiplexer outputs are translated from ECL to TTLby level shifter 92 having units 92a, 92b, 92c and 92d and therespective outputs of the last mentioned chip are applied to the "A" and"B" input ports of processor chip 56. Thus, level shift unit 92aprovides inputs to "A" terminals of unit 56, PAO:3; unit 92b, PA4:7,unit 92c, to "B" terminals, PBO:3; unit 92d, PB4.

CALIBRATION

With continued reference to FIG. 4, the hard-wired 13 bit digital wordrepresents a calibration frequency of 100 MHz in the present operativetester. The frequency of the test head oscillator with a short circuitplaced in the delay line socket is calibrated to be precisely 100 MHz bydoing a continuous comparison of the test head oscillator frequency tothe preset digital word and manually adjusting a variable capacitor 40(FIG. 3) to achieve such comparison.

Microprocessor 54 is designed to run only one program. However, thedigital delay line tester has two modes of operation, selected by theposition of the RUN/CALIBRATE switch 90. With the switch 90 in theCALIBRATE position, only the signal frequency on the multiplexer "A"terminals, derived from the test head oscillator output is permitted topass through the multiplexer 86. The select line 88 to the multiplexer86 is kept "low". By ensuring that the outputs of the multiplexer willnot change, the latch/comparator circuits 94 will provide an indicationthat calibration has been accomplished. The latch circuits 94a receive 8bits of data representing the test head output from selected levelshifter or output lines, S1 to S8 inclusive, and apply them to the "A"input terminals of the comparator 94b. Likewise 8 bits of the presentword representative of the 100 MHz calibration frequency are read intoin the "B" register of the comparator 94b. When the "A" word and the "B"word correspond to each other, the comparator outputs a signal to theLED indicator 96. That is, when the test head oscillator is running atexactly 100 MHz (as a result of manual fine tuning of capacitor 40), theLED indicator 96 lights and calibration is verified. It should be notedthat in the operative tester, satisfactory calibration was effectedusing only 8 of the 13 bits in the respective digital words, althoughmore than 8 bits may be used if desired.

AND gate 98 at the entrance to the comparator circuits cooperates withthe output of flip-flop 100 on line 102 to guarantee that thecomparator/latch 94 is only operational when the test head frequencycount is valid. The valid time is derived from two outputs of processorelement 56, namely, signals on the TIMER OUT and PORT C, PC1 terminals.

OPERATION

When switch 90 is placed in the RUN position, the microprocessor 54constantly changes the level on the select line 88 of the multiplexer86. When the line is "low", the microprocessor 54 reads in, through themultiplexer 86, the test head frequency that represents the delay lineunder test. When the select line 88 is "high", the microprocessor 54reads in the preset digital word on the multiplexer "B" terminals thatcorresponds to 100 MHz.

Before proceeding with the operations performed by the microprocessor indetermining the delay time of the line being tested, it may be helpfulto review some pertinent equations.

The frequency of the square wave signal out of the test head, V out (t),is equal to 1/2d where 2d is the period of the square wave cycle and istwice the delay in the loop. As noted hereinbefore, the test head loopcontains an implicit delay, dc, (with the test socket terminals shorted)and the frequency "fc" (100 MHz in the present embodiment) is equal to1/2dc. Accordingly, the measured frequency, fm, is equal to 1/2(dc+dx).Solving for dx, the delay of the line under test, yields the followingequation: ##EQU3## where dx is in seconds; fm, fc, in Hz.

With the foregoing equations as background, the microprocessor 54 isprogrammed to solve the following equation: ##EQU4## where d'x is inunits of 10 picoseconds or 10⁻¹¹ seconds; f'm and f'c are in Hz dividedby 32,000. The constant 1,562,500 is derived as follows. As notedhereinbefore, the counter-size and sensitivities were limited toreasonable numbers, by dividing the input frequencies by 32,000. Forexample, if fc=100 MHz then ##EQU5## which is the hard-wired preset wordin decimal mentioned hereinbefore. The constant "K" is necessary toreconcile the units chosen to represent the delay time. Thus, ##EQU6##Since our original equation for ##EQU7## Returning to the originalequation above for d'x and substituting 3,125,000 for K, we arrive atthe equation to be solved, namely ##EQU8##

The program strategy of the microprocessor 54 is as follows:

1. Read in the 13 bit number from the test head.

2. Read in the 13 bit preset word.

3. Solve the equation for d'x.

4. Convert the binary numeral to decimal.

5. Display the decimal value of the delay line.

6. Go to step 1.

Steps 1 and 2 above are accomplished by outputting from themicroprocessor 54 to the processor element 56 Port "C" output lines thecorrect sequence of four bit words. These control signals along with theTIMER OUT signal from element 56 perform the switching between thereference preset digital 100 MHz word and the test head frequencydependent upon the unknown delay, as well as division by 1,000 in thecounter 50. The TIMER OUT signal is a precise 1.0 kHz square waveproduced by element 56 from its TIMER IN signal, which comes fromdivider 76, which generates the divided microprocessor clock. Now, byonly enabling the counter 50 to count for 1.0 millisecond, an effectivedivision by 1,000 is done. The division by 32 is accomplished byignoring the first five counter outputs, lines Z1, Z2, Z3, Z4 of counter50a and line X5 of counter unit 50b.

Step 3 is implemented with a non-restoring division algorithm inaccordance with the microprocessor machine code stored in the PROM 60and accessed via latch 58. Scratch pad and long-term memory are inelement 56.

Step 4 is accomplished with software in the microprocessor 54.

Step 5 is implemented with hexidecimal latch/display elements 104 and106. Decoder 108 handles all of the bus traffic.

Step 6 is accomplished with a "jump" command.

In conclusion, the delay line tester of the present invention providesan accurate measure of delay lines in the nanosecond and subnanosecondrange. The measurements are made with considerable savings of test time.The circuit elements and parameters associated therewith, as presentedhereinbefore, refer to an actual operative tester; are submitted solyfor purposes of example; and are not to be construed as limitative ofthe invention. Changes and modifications of the circuit organizationpresented herein may be needed to suit particular requirements. Forexample, the microprocessor 54 utilized in the tester is a TTL type8085; the element 56, type 8156; and latch 58, 8212. These may bereplaced with ECL processor elements, thereby eliminating all thoseelements described herein as level shifters or converters. Similarly, areference frequency other than 100 MHz may be used, and a frequencydivision, other than 32,000, might be utilized, notwithstanding the factthat the foregoing parameters have produced highly satisfactory results.In view of the foregoing, all changes and modifications as are wellwithin the skill of the circuit designer, insofar as they are notdepartures from the true scope and spirit of the invention, are intendedto be covered by the following claims.

What is claimed is:
 1. A tester for measuring the value of the delaypresent in an unknown delay line comprising:a test head having afree-running square wave oscillator configured in a circuit loop, meansfor selectively coupling said unknown delay line into said circuit loop,said oscillator including inverter means and having oscillatorfine-tuning means for effecting a predetermined calibration frequency inthe absence of said unknown delay line in said circuit loop, means fordetermining the frequency of the square wave signals generated by saidoscillator, whereupon the coupling of said unknown delay line into saidcircuit loop causes the frequency of said oscillator to change from saidcalibration frequency to a measured frequency in direct proportion tothe value of the delay introduced into said circuit loop by said unknowndelay line, said last mentioned value being equal to one half of thedifference in the periods of the respective square wave signals at saidcalibration and measured frequencies.
 2. A tester as defined in claim 1wherein said frequency of the square wave signals generated by saidoscillator is a function of the delay in said inverter means, apredetermined length of coaxial cable forming a portion of said circuitloop and said oscillator fine-tuning means.
 3. A tester as defined inclaim 2 wherein said oscillator fine-tuning means is a variablecapacitor.
 4. A tester as defined in claim 3 wherein said means forselectively coupling said unknown delay line into said circuit loopincludes a pair of spaced-apart terminals disposed in said loop wherebya discontinuity is provided in the electrical path of said loop,electrical conductor means for short circuiting said terminals when saidtester is in a calibration mode, said unknown delay line being connectedacross said terminals when said tester is in an operation mode.
 5. Atester as defined in claim 4 wherein said inverter means comprises atransistor having an emitter, a collector, and a base electrode, saidtransistor being coupled in an inverting common emitter configuration,said circuit loop coupling said collector electrode to said baseelectrode, said emitter electrode being coupled to a source of referencepotential.
 6. A tester as defined in claim 5 wherein said predeterminedlength of coaxial cable couples said collector electrode of saidtransistor to one of said pair of spaced-apart terminals, said variablecapacitor being coupled between said last mentioned one of saidterminals and said source of reference potential.
 7. A tester as definedin claim 4 further including counter means coupled to said oscillatorfor dividing the frequency of said square wave signals by apredetermined factor, multiplexer means having a first and a secondplurality of terminals, said first plurality of multiplexer terminalsbeing coupled to said counter means for receiving a first digital wordrepresentative of the oscillator frequency, means for coupling a secondpreset digital word representative of said calibration frequency intosaid second plurality of multiplexer terminals, and control meanscoupled to said multiplexer means for selectively outputting said firstand second digital words from said multiplexer means.
 8. A tester asdefined in claim 7 further including comparator means operativelycoupled to said multiplexer means whereby at least respective homologousportions of said first and second digital words are compared to eachother during said tester calibration mode, said oscillator frequency andsaid first digital word being varied in response to the circuitcapacitance provided by said variable capacitor, and means coupled tosaid comparator means for indicating the correspondence of said firstand second digital words, thereby confirming the attainment of saidpredetermined calibration frequency.
 9. A tester as defined in claim 8further characterized in that said control means comprises processormeans, said processor means being operatively coupled to receive saidfirst digital word representative of said measured frequency during saidtester operation mode and said second preset digital word representativeof said calibration frequency, whereby said processor means performs arepetitive calculation of the delay of said unknown delay line by firstinverting and then subtracting said first and second digital words fromeach other, multiplying the remainder by a constant derived from thefrequency division effected by said counter means and the predeterminedunits in which said delay is presented, and further converting saiddelay from a binary to a decimal form.
 10. A tester as defined in claim9 further including display means coupled to said processor means fordisplaying said delay of said unknown delay line.
 11. A tester asdefined in claim 10 further characterized in that said calibrationfrequency is 100 MHz. and the numerical value of the frequency divisioneffected by said counter means is 32,000.